<?xml version="1.0" encoding="utf-8"?>
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.1//EN" "http://www.w3.org/TR/xhtml11/DTD/xhtml11.dtd">
<html xmlns="http://www.w3.org/1999/xhtml">
  <head>
    <title>CNTKCTL</title>
    <link href="insn.css" rel="stylesheet" type="text/css"/>
  </head>
  <body><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="AArch32-regindex.html">AArch32 Registers</a></div></td><td><div class="topbar"><a href="AArch64-regindex.html">AArch64 Registers</a></div></td><td><div class="topbar"><a href="AArch32-sysindex.html">AArch32 Instructions</a></div></td><td><div class="topbar"><a href="AArch64-sysindex.html">AArch64 Instructions</a></div></td><td><div class="topbar"><a href="enc_index.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="ext_alpha_index.html">External Registers</a></div></td><td><div class="topbar"><a href="ext_enc_index.html">External Registers by Offset</a></div></td><td><div class="topbar"><a href="func_index.html">Registers by Functional Group</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h1 class="register-section">CNTKCTL, Counter-timer Kernel Control register</h1><p>The CNTKCTL characteristics are:</p><h2>Purpose</h2>
        <p>Controls the generation of an event stream from the virtual counter, and access from EL0 modes to the physical counter, virtual counter, EL1 physical timers, and the virtual timer.</p>
      <h2>Configuration</h2><p>AArch32 System register CNTKCTL bits [31:0] are architecturally mapped to AArch64 System register <a href="AArch64-cntkctl_el1.html">CNTKCTL_EL1[31:0]</a>.</p><p>This register is present only when EL1 is capable of using AArch32. Otherwise, direct accesses to CNTKCTL are <span class="arm-defined-word">UNDEFINED</span>.</p><h2>Attributes</h2>
        <p>CNTKCTL is a 32-bit register.</p>
      <h2>Field descriptions</h2><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="lr" colspan="14"><a href="#fieldset_0-31_18">RES0</a></td><td class="lr" colspan="1"><a href="#fieldset_0-17_17-1">EVNTIS</a></td><td class="lr" colspan="7"><a href="#fieldset_0-16_10">RES0</a></td><td class="lr" colspan="1"><a href="#fieldset_0-9_9">PL0PTEN</a></td><td class="lr" colspan="1"><a href="#fieldset_0-8_8">PL0VTEN</a></td><td class="lr" colspan="4"><a href="#fieldset_0-7_4">EVNTI</a></td><td class="lr" colspan="1"><a href="#fieldset_0-3_3">EVNTDIR</a></td><td class="lr" colspan="1"><a href="#fieldset_0-2_2">EVNTEN</a></td><td class="lr" colspan="1"><a href="#fieldset_0-1_1">PL0VCTEN</a></td><td class="lr" colspan="1"><a href="#fieldset_0-0_0">PL0PCTEN</a></td></tr></tbody></table><h4 id="fieldset_0-31_18">Bits [31:18]</h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-17_17-1">EVNTIS, bit [17]<span class="condition"><br/>When FEAT_ECV is implemented:
                        </span></h4><div class="field">
      <p>Controls the scale of the generation of the event stream.</p>
    <table class="valuetable"><tr><th>EVNTIS</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>The CNTKCTL.EVNTI field applies to <a href="AArch32-cntvct.html">CNTVCT</a>[15:0].</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>The CNTKCTL.EVNTI field applies to <a href="AArch32-cntvct.html">CNTVCT</a>[23:8].</p>
        </td></tr></table>
      <p>This control applies regardless of the value of the <a href="AArch64-cnthctl_el2.html">CNTHCTL_EL2</a>.ECV bit.</p>
    <p>The reset behavior of this field is:</p><ul><li>On a Warm reset, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><h4 id="fieldset_0-17_17-2"><span class="condition"><br/>Otherwise:
                        </span></h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-16_10">Bits [16:10]</h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-9_9">PL0PTEN, bit [9]</h4><div class="field">
      <p>Traps PL0 accesses to the physical timer registers to Undefined mode.</p>
    <table class="valuetable"><tr><th>PL0PTEN</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>PL0 accesses to the <a href="AArch32-cntp_ctl.html">CNTP_CTL</a>, <a href="AArch32-cntp_cval.html">CNTP_CVAL</a>, and <a href="AArch32-cntp_tval.html">CNTP_TVAL</a> registers are trapped to Undefined mode.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>This control does not cause any instructions to be trapped.</p>
        </td></tr></table><p>The reset behavior of this field is:</p><ul><li>On a Warm reset, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><h4 id="fieldset_0-8_8">PL0VTEN, bit [8]</h4><div class="field">
      <p>Traps PL0 accesses to the virtual timer registers to Undefined mode.</p>
    <table class="valuetable"><tr><th>PL0VTEN</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>PL0 accesses to the <a href="AArch32-cntv_ctl.html">CNTV_CTL</a>, <a href="AArch32-cntv_cval.html">CNTV_CVAL</a>, and <a href="AArch32-cntv_tval.html">CNTV_TVAL</a> registers are trapped to Undefined mode.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>This control does not cause any instructions to be trapped.</p>
        </td></tr></table><p>The reset behavior of this field is:</p><ul><li>On a Warm reset, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><h4 id="fieldset_0-7_4">EVNTI, bits [7:4]</h4><div class="field"><p>Selects which bit of <a href="AArch32-cntvct.html">CNTVCT</a>, as seen from EL1, is the trigger for the event stream generated from that counter when that stream is enabled.</p>
<p>If <span class="xref">FEAT_ECV</span> is implemented, and CNTKCTL.EVNTIS is 1, this field selects a trigger bit in the range 8 to 23 of <a href="AArch32-cntvct.html">CNTVCT</a>.</p>
<p>Otherwise, this field selects a trigger bit in the range 0 to 15 of <a href="AArch32-cntvct.html">CNTVCT</a>.</p><p>The reset behavior of this field is:</p><ul><li>On a Warm reset, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><h4 id="fieldset_0-3_3">EVNTDIR, bit [3]</h4><div class="field">
      <p>Controls which transition of the <a href="AArch32-cntvct.html">CNTVCT</a> trigger bit, as seen from EL1 and defined by EVNTI, generates an event when the event stream is enabled.</p>
    <table class="valuetable"><tr><th>EVNTDIR</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>A 0 to 1 transition of the trigger bit triggers an event.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>A 1 to 0 transition of the trigger bit triggers an event.</p>
        </td></tr></table><p>The reset behavior of this field is:</p><ul><li>On a Warm reset, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><h4 id="fieldset_0-2_2">EVNTEN, bit [2]</h4><div class="field">
      <p>Enables the generation of an event stream from <a href="AArch32-cntvct.html">CNTVCT</a> as seen from EL1.</p>
    <table class="valuetable"><tr><th>EVNTEN</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>Disables the event stream.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>Enables the event stream.</p>
        </td></tr></table><p>The reset behavior of this field is:</p><ul><li>On a Warm reset, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><h4 id="fieldset_0-1_1">PL0VCTEN, bit [1]</h4><div class="field">
      <p>Traps PL0 accesses to the frequency register and virtual counter register to Undefined mode.</p>
    <table class="valuetable"><tr><th>PL0VCTEN</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td><p>PL0 accesses to the <a href="AArch32-cntvct.html">CNTVCT</a> are trapped to Undefined mode.</p>
<p>PL0 accesses to the <a href="AArch32-cntfrq.html">CNTFRQ</a> register are trapped to Undefined mode, if <a href="AArch32-cntkctl.html">CNTKCTL</a>.PL0PCTEN is also 0.</p></td></tr><tr><td class="bitfield">0b1</td><td>
          <p>This control does not cause any instructions to be trapped.</p>
        </td></tr></table><p>The reset behavior of this field is:</p><ul><li>On a Warm reset, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><h4 id="fieldset_0-0_0">PL0PCTEN, bit [0]</h4><div class="field">
      <p>Traps PL0 accesses to the frequency register and physical counter register to Undefined mode.</p>
    <table class="valuetable"><tr><th>PL0PCTEN</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td><p>PL0 accesses to the <a href="AArch32-cntpct.html">CNTPCT</a> are trapped to Undefined mode.</p>
<p>PL0 accesses to the <a href="AArch32-cntfrq.html">CNTFRQ</a> register are trapped to Undefined mode, if <a href="AArch32-cntkctl.html">CNTKCTL</a>.PL0VCTEN is also 0.</p></td></tr><tr><td class="bitfield">0b1</td><td>
          <p>This control does not cause any instructions to be trapped.</p>
        </td></tr></table><p>The reset behavior of this field is:</p><ul><li>On a Warm reset, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><div class="access_mechanisms"><h2>Accessing CNTKCTL</h2><p>Accesses to this register use the following encodings in the System register encoding space:</p><h4 class="assembler">MRC{&lt;c&gt;}{&lt;q&gt;} &lt;coproc&gt;, {#}&lt;opc1&gt;, &lt;Rt&gt;, &lt;CRn&gt;, &lt;CRm&gt;{, {#}&lt;opc2&gt;}</h4><table class="access_instructions"><tr><th>coproc</th><th>opc1</th><th>CRn</th><th>CRm</th><th>opc2</th></tr><tr><td>0b1111</td><td>0b000</td><td>0b1110</td><td>0b0001</td><td>0b000</td></tr></table><p class="pseudocode">
if PSTATE.EL == EL0 then
    UNDEFINED;
elsif PSTATE.EL == EL1 then
    R[t] = CNTKCTL;
elsif PSTATE.EL == EL2 then
    R[t] = CNTKCTL;
elsif PSTATE.EL == EL3 then
    R[t] = CNTKCTL;
                </p><h4 class="assembler">MCR{&lt;c&gt;}{&lt;q&gt;} &lt;coproc&gt;, {#}&lt;opc1&gt;, &lt;Rt&gt;, &lt;CRn&gt;, &lt;CRm&gt;{, {#}&lt;opc2&gt;}</h4><table class="access_instructions"><tr><th>coproc</th><th>opc1</th><th>CRn</th><th>CRm</th><th>opc2</th></tr><tr><td>0b1111</td><td>0b000</td><td>0b1110</td><td>0b0001</td><td>0b000</td></tr></table><p class="pseudocode">
if PSTATE.EL == EL0 then
    UNDEFINED;
elsif PSTATE.EL == EL1 then
    CNTKCTL = R[t];
elsif PSTATE.EL == EL2 then
    CNTKCTL = R[t];
elsif PSTATE.EL == EL3 then
    CNTKCTL = R[t];
                </p></div><hr class="bottom_line"/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="AArch32-regindex.html">AArch32 Registers</a></div></td><td><div class="topbar"><a href="AArch64-regindex.html">AArch64 Registers</a></div></td><td><div class="topbar"><a href="AArch32-sysindex.html">AArch32 Instructions</a></div></td><td><div class="topbar"><a href="AArch64-sysindex.html">AArch64 Instructions</a></div></td><td><div class="topbar"><a href="enc_index.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="ext_alpha_index.html">External Registers</a></div></td><td><div class="topbar"><a href="ext_enc_index.html">External Registers by Offset</a></div></td><td><div class="topbar"><a href="func_index.html">Registers by Functional Group</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">30/03/2023 19:07; 997dd0cf3258cacf72aa7cf7a885f19a4758c3af</p><p class="copyconf">Copyright © 2010-2023 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.</p></body>
</html>
